1. Field of the Invention
This invention relates generally to digital integrated circuits, and in particular, to an improved apparatus and method for distributing and controlling clock pulses, and minimizing clock skew thereof, in a digital integrated circuit.
2. Description of the Related Technology
Semiconductor integrated circuits comprise the majority of electronic circuits in computers and other digital electronic products. Present technology integrated circuits may contain millions of transistors and be configured, for example, as a central processing unit (CPU), arithmetic logic unit (ALU), random access memory (RAM), programmable logic array (PLA), application specific integrated circuit (ASIC), or digital signal processor (DSP). Both sophistication and speed of operation of these integrated circuits have rapidly increased because of improvements in integrated circuit manufacturing technologies resulting in smaller and faster devices.
In complex digital integrated circuits, a clock signal is normally required to operate multistate logic circuits such as the aforementioned CPU, ALU, RAM, PLA, ASIC, and DSP integrated circuits. The clock signal must be distributed throughout the integrated circuit chip to logic circuits contained therein. Multiple clock signals may be desired or required depending on the functionality of the integrated circuit.
Design of complex integrated circuits is accomplished by computer simulation which allows the integrated circuit designer to easily implement and test his design before committing it to silicon. In designing the integrated circuit layout by computer, one of the requirements is to distribute the aforementioned clock signals. These clock signals must be routed from the clock input pad which will be connected to a leadframe lead that is used as an external clock pin input and connects to an external system circuit board having a computer system clock thereon. The clock signal from the clock input pad is routed by means of a main trunk that feeds tributaries. The tributaries in turn drive loads requiring the clock signal.
Clock distribution technology utilizes a main trunk with tributaries branching out from the main trunk as needed for connection to the logic within the integrated circuit chip. Depending on the loading requirements of the integrated circuit logic, active device buffer circuits are used to drive the various integrated circuit loads.
Referring to FIGS. 1 through 3, prior art clock distribution systems are illustrated in schematic block diagram. An integrated circuit chip die 10 is comprised of logic circuits (not illustrated). Some of the logic circuits require a clock signal to function. The clock signal may be generated off the chip 10 and connected to an exterior clock input pin 12. The input pin 12 connects through, for example, a lead frame (not illustrated) to a buffer 14. The output of buffer 14 connects to a clock distribution trunk 16. Trunk buffers 14a and 14b have been used to more evenly distribute clock drive to both ends of the trunk 16.
The trunk 16 has a plurality of tributaries 18 connected thereto. Branches 20 connect the loads (not illustrated) to the clock signal tributaries 18. When the loads require increased clock signal power, tributary buffers 15 have been used.
All electronic circuit loads have resistance, inductance and capacitance inherent with the physical structure of the electronic circuit. Integrated circuit devices have predominately resistance and capacitance. The resistance ("R") and capacitance ("C") create an RC time constant delay to a fast rising edge square wave, such as a clock signal. When clock signal delays are different between different areas of the integrated circuit, then the difference between the signal delays is called "skew".
Differences in clock signal delays are usually caused by differences in capacitance associated with the different circuit loads requiring the clock signal. Reliable operation of complex electronic circuits within an integrated circuit depends upon data being stable when a clock signal is received. If a clock signal is delayed, then the data may no longer be valid. Clock skew within an integrated circuit was not a major problem until the speed of integrated circuits increased dramatically.
An integrated circuit working at 10 mHz has a clock rate of 100 nanoseconds. An integrated circuit operating at 100 mHz requires a clock rate of 10 nanoseconds. The clock distribution illustrated in FIGS. 1-3 may have a clock skew of 2 nanoseconds. 2 nanoseconds at a clock rate of 100 nanoseconds is not significant, however, at a clock rate of 10 nanoseconds, it is a 20 percent variation which is significant.
Another problem with the clock distribution illustrated in FIGS. 1-3 is the difficulty in evenly distributing or balancing the capacitive loading of the integrated circuit devices. This is especially a problem when distributing clock signals to megabit random access memory ("megaram"). The megaram is so large and takes up so much space on the integrated circuit chip that clock signal routing for minimum skew is a problem.